WebEE

fc	fu	fl	BW	Q
113	160	80	80	1.414
226	320	160	160	1.414
453	640	320	320	1.414
905	1280	640	640	1.414
1,810	2560	1280	1280	1.414
3,620	5120	2560	2560	1.414
7,241	10240	5120	5120	1.414
14,482	20480	10240	10240	1.414

Table 1 - Bandpass Filter Characteristics

Figure 8 shows the frequency response of each of the eight filters overlapped on the same graph. Specific clocking and C-value information can be found in Appendix B. Except for the 15Khz filter, the C values are identical for each combination – only the clock is changed. To avoid overclocking, the C values had to be changed for the 15Khz filter. That is why its response peaks slightly higher than the other filters.

The software switches sequentially between the filter configurations giving each one a specific period to settle and a specific sample period. The lower frequency filters need more time to settle and a longer sampling period than the high frequency filters.

• Figure 8 - Response of the Eight Bandpass Filters

Following the filters is the EQU AMP (ACA02) or equalization amp. This amplifier provides a unique gain for each filter combination so that flat frequency response will be observed for an ideal system. Not shown is an additional gain boost amplifier in block ACA03.

The band pass filtered, analog signal is then fed into the DELSIG8 A/D. This device is clocked at 8Mhz to provide a sample rate of 31.25Kz. Although this sample rate is below the Nyquist rate for signals greater than 15Khz, it is acceptable in our application since we are not using the samples as a representation of the waveform.

As the A/D values become available, a software peak detector is employed to save the sample with the greatest absolute value during the period for each filter. At the conclusion of the filter period, the high value is saved in an eight-register circular buffer. The average of the eight previous readings is then calculated and saved. The upper three bits of this value are used as an index into a lookup table that contains the bar-graph patterns for the 8X8 LED display. An array of eight bytes is used to store the pattern for each spectral band.

The display driver is an interrupt service routine that occurs 800 times per second. During each pass of the routine, a single column of the display is driven. With 8 columns and an update rate of 800 columns per second, the entire display is updated 100 times per second.

External transistors are used as column drivers while individual port pins drive the rows. The circuit depends on the maximum current of 25mA for the port pins to control the drive to the row LEDs.

Code Description
The code has two fundamental modules: the main loop and the 40Khz Timer Tick. These modules are described in more detail below.